The present invention generally relates to semiconductor packages and more particularly to semiconductor packages and methods of making semiconductor packages.
In many MOSFET switching circuits a pair of power MOSFETs is switched in complementary fashion. A typical MOSFET switching circuit 10 is shown in FIG. 1 and includes two MOSFETs 12 and 14 coupled in series across a voltage source Vin and ground. MOSFETs 12 and 14 are typically referred to as high side and low side MOSFETs, respectively.
To initiate a switching cycle, MOSFET 14 is first turned off. As a result, the body diode of MOSFET 14 turns-on and drives current. After a delay, MOSFET 12 turns on, turning-off the body diode of MOSFET 14. This generates a recovery current IL through, as well as, trace inductances (not shown) associated with switching circuit 10, producing oscillations.
In order to save space and cost, MOSFETs 12 and 14 are often co-packaged together, as indicated by a dashed line. It is the goal of MOSFETs 12 and 14 to attain the highest power density possible in order to work efficiently. The power density is closely related to the die area, i.e., the larger the die, the lower the drain-to-source on resistance, Rdson. Typically, MOSFETs 12 and 14 are co-packaged side by side, on separate die pads, as shown in FIG. 2. The overall package outline is indicated by the dashed line. Conventional power MOSFETs 12 and 14 are vertical devices, with the source S1 and S2, respectively, and gate, G1 and G2, respectively, on one side, and the drain, D1 and D2, respectively, on an opposing side. MOSFET 12 is attached to a die pad 16, which has leads extending from it allowing connection to drain D1. MOSFET 14 is attached to a die pad 18. The low side die pad can be exposed through the bottom of a dual flat non-leaded (DFN) package for external connection to drain D2 and source S1. Typically low side MOSFET 14 has a larger die area, compared to high side MOSFET 12, because MOSFET 14 is usually turned on for a longer duration of time. Source S1 contacts drain D2 by way of bond wires from S1 to die pad 18. Gates G1 and G2, as well as source S2 are connected to the appropriate leads by bond wires. The die areas of MOSFETs 12 and 14 are constrained by the package size and by the side by side configuration of the dies.
Therefore, a need exists to improve the operational performance by maximizing the die area of MOSFETs to minimize Rdson without unduly increasing the overall size of the circuit.